Semiconductor memories technology testing and reliability free pdf

Ashok K. Sharma Silver Spring, Maryland Semiconductor Memories Introduction Semiconductor memories are usually consid- ered to be the most vital microelectronic com- ponent of digital logic system design, such as computers and microprocessor-based applica- tions ranging from satellites to consumer elec- tronics.

Therefore, advances in the fabrication of semiconductor memories including process enhancements and technology developments through the scaling for higher densities and faster speeds help establish performance stan- dards for other digital logic families.

Semicon- ductor memory devices are characterized as volatile random access memories or nonvolatile memory devices. In RAMs, the logic information is stored either by setting up the logic state of a bistable flip-flop such as in a static random access memory SRAM , or through the charging of a capacitor as in a dy- namic random access memory DRAM. In ei- ther case, the data are stored and can be read out as long as the power is applied, and are lost when the power is turned off; hence, they are called volatile memories, Nonvolatile memories are capable of stor- ing the data, even with the power turned off.

The nonvolatile memory data storage mode may be permanent or reprogrammable, depending upon the fabrication technology used. Nonvolatile memories are used for program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications, and 1 consumer electronics industries.

A combination of single-chip volatile as well as nonvolatile memory storage modes is also available in de- vices such as nonvolatile SRAM nvRAM for use in systems that require fast, reprogrammable nonvolatile memory. In addition, dozens of spe- cial memory architectures have evolved which contain some additional logic circuitry to opti- mize their performance for application-specific tasks. This book on semiconductor memories covers random access memory technologies SRAMs and DRAMs and their application- specific architectures; nonvolatilememorytech- nologies such as read-only memories ROMs , programmable read-only memories PROMs , and erasable and programmable read-only memories EPROrvls in both ultraviolet eras- able UVPROM and electrically erasable EEPROM versions; memory fault modeling and testing; memory design for testability and fault tolerance; semiconductor memory reliabil- ity; semiconductor memory radiation effects; advanced memory technologies; and high- density memory packaging technologies.

Chapter 2 on "Random Access Memory Technologies," reviews the static and dynamic RAM technologies as well as their application- specific architectures. In the last two decades of semiconductor memory growth, the DRAMs have been the largest volume volatile memory 1 2 produced for use as main computer memories because of their high density and low cost per bit advantage.

Therefore, in high-density and high-speed applications, various combinations of bipolar and MOS technologies are being used. In addition to the MaS and bipolar mem- ories referred to as the "bulk silicon" tech- nologies, silicon-on-insulator SOl isolation technology such as silicon-on-sapphire SOS SRAMs have been developed for improved ra- diation hardness. The SRAM density and per- formance are usually enhanced by scaling down the device geometries. Advanced SRAM de- signs and architectures for 4 and 16 Mb density chips with submicron feature sizes e.

Application-specific mem- ory designs include first-in first-out FIFO , which is an example of shift register memory ar- chitecture through which the data are trans- ferred in and out serially. The dual-port RAMs allow two independent devices to have simulta- neous read and write access to the same mem- ory. Special nonvolatile, byte-wide RAM configurations require not only very low oper- ating power, but have battery back-up data- retention capabilities.

The content-addressable memories CAMs are designed and used both as the embedded modules on larger VLSI chips and as stand-alone memory for specific system applications. A significant improvement in DRAM evolution has been the switch from three-transistor 3-T designs to one-transistor 1-T cell design that has enabled production of 4 and 16 Mb density chips that use advanced, 3-D trench capacitor and stacked capacitor cell structures.

The DRAMs are susceptible to soft errors or cell logic upset occurring from alpha particles produced by trace radioactive packag- ing material. Chapter 3 reviews various nonvolatile memory NVM technologies. In , a floating polysilicon- gate-based erasable programmable read-only memory was developed in which hot electrons are injectedinto the floatinggate and removedei- ther by ultraviolet internal photoemission or Fowler-Nordheimtunneling. Several technology advances in cell structures, scaling, and process enhancements have made possible the fabrication of Mb density EPROMs.

The conventional, full functional EEPROMs have several advan- tages, including the byte-erase, byte-program, andrandom accessreadcapabilities. The flash memories, because of their bulk erase characteristics, are unlike the floating-gate EEPROMs whichhaveselect transistors incorpo- rated in each cell to allowfor the individual byte erasure. The improve- ments in flash EEPROMcell structures have re- sulted in the fabrication of 8 and 16 Mb density devices for use in high-density nonvolatile stor- age applications such as memory modules and memory cards.

Chapter 4 on "Memory Fault Modeling and Testing," reviews memory failure modes and mechanisms, fault modeling, and electrical testing. The memory device failures are usually representedby a bathtub curve and are typically grouped into three categories, depending upon the product's operatinglife cycle stage where the failures occur. A most commonly used model is the single-stuck-at fault SSF which is also re- ferred to as the classical or standardfault model.

However, the major shortcomingof the stuck-at fault model is that the simulation using this model is no longer an accurate quality indicator for the ICs like memory chips. A large percent- age of physical faults occurringin the ICs can be considered as the bridging faults BFs consist- ing of shorts between two or more cells or lines.

Another important category of faults that can cause the semiconductor RAM cell to function erroneouslyis the couplingor PSFs. Many algorithms have been proposed for the neighborhood pattern-sensitive faults NPSFs based on an assumption that the memory array's physical and logical neighborhoods are identical.

This may not be a valid assumption in state-of- the-art memory chips which are being designed with the spare rows and columns to increase yield and memory array reconfiguration, if needed. The embedded RAMs which are being used frequently are somewhat harder to test be- cause of their limited observability and control- lability. A defect-oriented inductive fault analysis has been shown to be quite useful in finding various defect mechanisms for a given layout and technology.

For RAMs, various functional test algorithms have been developed for which the test time is a function of the number of memory bits n and range in complexity from O n to 0 n 2. The selection of a particular set of test patterns for a given RAM is influenced by the type of failure modes to be detected, mem- ory bit density which influences the test time, and the memory ATE availability. These are the deterministic techniques which require well- defined algorithms and memory test input pat- terns with corresponding measurements of expected outputs.

An alternate test approach often used for the memories is random or pseudorandom testing which consists of apply- ing a string of random patterns simultaneously to a device under test and to a reference mem- ory, and comparing the outputs. Advanced megabit memory architectures are being de- signed with special features to reduce test time by the use of the multibit test MBT , line mode test LMT , and built-in self-test BIST. Recent stud- ies have shown that monitoring of the elevated quiescent supply currents IDDQ appears to be a good technique for detecting the bridging fail- ures.

In general, the memory testability is a function of variables such as cir- cuit complexity and design methodology. The Chap. The various methodologies for the BIST include exhaustive testing, pseudo- random testing, and the pseudoexhaustive test- ing. The major advan- tages associated with a microcoded ROM over the use of random logic are a shorter design cycle, the ability to implement alternative test algorithms with minimal changes, and ease in testability of the microcode.

The current generation mega- bit memory chips include spare rows and columns redundancies in the memory array to compensate for the faulty cells. In addition, to Chap. The conventional ex- haustive test schemes for the ROMs use com- paction techniques which are parity-based, count-based, or polynomial-division-based sig- nature analysis.

The err-ors in semiconductor memories can be broadly categorized into hard failures caused by permanent physical damage to the de- vices, and soft errors caused by alpha particles or the ionizing dose radiation environments. The most commonly used error-correcting codes ECC which are used to correct hard and soft errors are the single-error-correction and double-error-detection SEC-DED codes, also referred to as the Hamming codes.

How- ever, these codes are inadequate for correcting double-bitlword-line soft errors. Advanced 16 Mb DRAM chips have been developed that use redundant word and bit lines in conjunction with the ECC to produce an optimized fault tol- erance effect. In a new self-checking RAM ar- chitecture, on-line testing is performed during normal operations without destroying the stored data.

A fault tolerance synergism for memory chips can be obtained by a combined use of re- dundancy and ECC. A RAM fault tolerance ap- proach with dynamic redundancy can use either the standby reconfiguration method, or memory reconfiguration by the graceful degradation scheme. To recover from soft errors transient effects , memory scrubbing techniques are often used which are based upon the probabilistic or deterministic models. Chapter 6 reviews general reliability is- sues for semiconductor devices such as the memories, RAM failure modes and mecha- nisms, nonvolatile memories reliability, reliabil- ity modeling and failure rate prediction, design for reliability, and reliability test structures.

The reliability of a semiconductor device such as a memory is the possibility that the device will 5 perform satisfactorily for a given time at a de- sired confidence level under specified operating and environmental conditions. The memory de- vice failures are a function of the circuit design techniques, materials, and processes used in fabrication, beginning from the wafer level probing to assembly, packaging, and testing.

The general reliability issues pertaining to semi- conductor devices in bipolar and MOS tech- nologies are applicable to the memories also, such as the dielectric-related failures from gate-oxide breakdown, time-dependent dielec- tric breakdown TDDB , and ESD failures; the dielectric-interface failures such as those caused by ionic contamination and hot carrier effects: the conductor and metallization failures, e.

How- ever, there are special reliability issues and failure modes which are of special concern for the RAMs. These issues include gate oxide reli- ability defects, hot-carrier degradation, the DRAM capacitor charge-storage and data-reten- tion properties, and DRAM soft-error failures.

The memory gate dielectric integrity and relia- bility are affected by all processes involved in the gate oxide growth. The reduced MaS transistor geometries from scaling of the memory devices has made them more susceptible to hot carrier degradation ef- fects. Nonvolatile memo- ries, just like volatile memories, are also suscep- tible to some specific failure mechanisms.

For PROMs with fusible links, the physical integrity and reliability of fusible links are a major con- cern. The ferroelectric memory reliability concerns include the aging effects of temperature, electric field, and the number of polarization reversal cycles on ferro- electric films used e.

Reliability failure modelingis a key to the failure rate predictions, and there are many sta- tistical distributions such as the Poisson, Normal or Gaussian , Exponential, Weibull, and Log- normal that are used to model various reliability parameters.

However, the failure rate calculation results for semiconductor memories may vary widely fromone model to another. De- sign for reliability DFR , which includes failure mechanisms modeling and simulation, is an im- portant concept that should be integrated with the overall routine process of design for perfor- mance.

The method of accelerated stress aging for semiconductor devices such as memories is commonly used to ensure long-term reliability.

For nonvolatile memories, endurance modeling is necessary in the DFR methodology. An ap- proach commonly employed by the memory manufacturers in conjunction with the end-of- line product testinghas been the use of reliability test structures and process or yield monitors in- corporatedat the wafer level in kerf test sites and "drop-in" test sites on the chip.

The purpose of reliabilitytesting is to quantify the expectedfail- ure rate of a device at various points in its life cycle.

The memory failure modes which can be accelerated by a combined elevated temperature and high-voltage stress are the threshold voltage shifts, TDDB leading to oxide shorts, and data- retention degradation for the nonvolatile memo- ries.

MIL-STD, Method Screening Procedure or equivalent are commonlyusedby the memory manufacturers to detect and elimi- nate the infant mortality failures. Chapter 7, entitled "Semiconductor Mem- ory Radiation Effects," reviews the radiation- hardeningtechniques,radiation-hardening design Chap. The space radiation environment poses a certain radiation risk to all electronic components on earth orbiting satellites and the planetary mis- sion spacecrafts.

Although the natural space en- vironment does not contain the high dose rate pulse characteristics of a weapon environment often referred to as the "gamma dot" , the cu- mulative effect of ionization damage from charged particles such as electrons and protons on semiconductor memories can be significant.

In general, the bipolar technology memories e. For the MOS devices, the ionization traps positive charge in the gate oxide called the oxide traps, and produces interface states at the Si-Si0 2 interface.

The magnitude of these changes depends upon a number of fac- tors such as total radiation dose and its energy; dose rate; applied bias and temperature during irradiation; and postirradiation annealing condi- tions. The single-event phenomenon SEP in the memories is caused by high-energy particles such as those present in the cosmic rays passing through the device to cause single-event upsets SEUs or soft errors, and single-event latchup SEL which may result in hard errors.

The im- pact of SEU on the memories, because of their shrinking dimensions and increasing densities, has become a significant reliability concern. The number of SEUs experienced by a mem- ory device in a given radiation environment depends primarily on its threshold for upsets, usually expressed by its critical charge Q c or the critical LET and the total device volume sensitive to ionic interaction, i.

The Q c is primarily correlated to circuit design characteristics. Criti- cal LET for a memory is found experimentally by bombarding the device with various ion Chap.

For the memory devices flown in space, radiation tolerance is as- sessed with respect to the projected total dose accumulated, which is the sum of absorbed dose contributions from all ionizing particles, and is calculated in the form of dose-depth curves by sophisticated environmental modeling based upon the orbital parameters, mission duration, and thickness of spacecraft shielding. It is im- portant to verify ground test results obtained by observation of actual device behavior in orbit.

Several in-orbit satellite experiments have been designed to study the effect of the radiation par- ticle environment on semiconductor devices such as memories.

The nonvolatile MOS memories are also subject to radiation degradation effects. The ra- diation hardness of memories is influenced by a number of factors, both process- and design-re- lated. The process-related factors which affect radiation response are the substrate effects, gate oxidation and gate electrode effects, post- polysilicon processing, and field oxide harden- ing.

The memory cir- cuits can be designed for total dose radiation hardness by using optimized processes e. Radiation sensitivity of unhardened mem- ory devices can vary from lot to lot, and for space applications, radiation testing is required to characterize the lot radiation tolerance. The ground-based radiation testing is based upon a simulation of space environment by using radia- tion sources such as the Cobalt, X-ray tubes, particle accelerators, etc. For example, total dose radiation testing on the memories is per- formed per MIL-STD, Method , which 7 defines the test apparatus, procedures, and other requirements for effects from the Co gamma ray source.

Radiation testing requires calibra- tion of the radiation source and proper dosime- try. Sometimes, radiation test structures are used at the wafer or chip level as process monitors for radiation hardness assurance. In the last few years, an area of interest in advanced non- volatile memories has been the development of thin-film ferroelectric FE technology that uses magnetic polarization or hysteresis properties to build the FRAMs.

The high-dielectric- constant materials such as lead zirconate titan- ate PZT thin film can be used as a capacitive, nonvolatile storage element similar to trench ca- pacitors in the DRAMs. This FE film technol- ogy can be easily integrated with standard semiconductor processing techniques to fabri- cate the FRAMs which offer considerable size and density advantage. A FRAM uses one tran- sistor and one capacitor cell.

Therefore, thermal stability, fatigue from polarization rever- sal cycling, and aging of the FRAMs are key re- liability concerns. In general, the FE capacitors and memories made from thin-film PZT have shown high-radiation-tolerance characteristics suitable for space and military applications.

The memory storage volatile or non- volatile usually refers to the storage of digital bits of information "O"s and "T's , However, recently, analog nonvolatile data storage has also been investigated using the EEPROMs and FRAMs in applications such as audio recording of speech and analog synaptic weight storage for neural networks. This nonvolatile analog 8 storage is accomplished by using the EEPROMs which are inherently analog memories on a cell- by-cell basis because each floating gate can store a variable voltage.

The sensed value of a cell's conductivity corresponds to the value of the analog level stored. This technology has been used in audio applications such as single- chip voice messaging systems. Another technol- ogy development for nonvolatile storage is the magnetoresistive memory MRAM which uses a magnetic thin-film sandwich configured in two-dimensional arrays.

These MRAMs are based upon the principle that a material's mag- netoresistance will change due to the presence of a magnetic field. Another variation on this technology is the design and conceptual development of micromagnet-Hall effect ran- dom access memory MHRAM where infor- mation is stored in small magnetic elements. The latest research in advanced memory tech- nologies and designs includes the solid-state de- vices that use quantum-mechanical effects such as resonant-tunneling diodes RTDs and reso- nant-tunneling hot-electron transistors RHETs for possible development of gigabit memory densities.

These devices are based upon the neg- ative resistance or negative differential conduc- tance property which causes a decrease in current for an increase in voltage. Chapter 9, "High-Density Memory Pack- aging Technologies," reviews commonly used memory packages, memory hybrids and 2-D multichip modules MCMs , memory stacks and 3-D MCMs, memory MCM testing and reli- ability issues, memory cards, and high-density memory packaging future directions.

The most common high-volume usage semiconductor RAMs and nonvolatile memories use "through- the-hole" or insertion mount and the surface mount technology SMT packages. For high- Chap. I Introduction reliability military and space applications, her- metically sealed ceramic packages are usually preferred. For high-density memory layouts on the PC boards, various types of packaging con- figurations are used to reduce the board level memory package "footprint.

For the assembly of MCMs, various interconnection technologies have been developed such as the wire bonding, tape automated bonding TAB , flip-chip bond- ing, and high-density interconnect HDI. Several variations on 3-D MCM technology have evolved for the memories, with a goal of improving storage den- sities while lowering the cost per bit.

The density of chip packaging expressed as the "silicon effi- ciency" is determined by the ratio of silicon die area to the printed circuit board or substrate area. In the chip-on-board COB packaging, the bare memory chip or die is di- rectly attached to a substrate, or even PC board such as FR4 glass epoxy. An extension of 2-D planar technology has been the 3-D concept in which the memory chips are mounted vertically prior to the attach- ment of a suitable interconnect. The" 3-D ap- proach can provide higher packaging densities because of reduction in the substrate size, mod- ule weight, and volume; lower line capacitance and drive requirements; and reduced signal propagation delay times.

Four generic types of Chap. However, MCM defects and failures can occur due to the materials, including the sub- strate, dice, chip interconnections, and manu- facturing process variations; lack of proper statistical process control SPC during fabrica- tion and assembly; inadequate screening and qualification procedures; and a lack of proper de- sign for testability OFT techniques. Another application for high-density memory bare chip assembly has been the devel- opment of memory cards that are lightweight plastic and metal cards containing the memory chips and associated circuitry.

They offer signifi- cant advantages in size, weight, speed, and power consumption. In high-density memory development, the future direction is to produce mass memory configurations of very high bit densities ranging from tens of megabytes to several hundred giga- bytes by integrating 3-D technology into the MCMs. In RAMs, the infor- mation is stored either by setting the state of a bistable flip-flop circuit or through the charging of a capacitor. In either of these methods, the in- formation stored is destroyed if the power is in- terrupted.

Such memories are therefore referred to as volatile memories. If the data are stored i. When a capacitor is used to store data in a semiconductor RAM, the charge needs to be periodically refreshed to prevent it from being drained through the leakage currents.

However, static RAMs are being widely used in systems today because of their low-power dissipation and fast data access time. SRAM speed has been usually enhanced by scaling of the MOS process since shorter gate channel length, L eft translates quite lin- early into faster access time. This scaling of the process from first -generation to second-generation SRAMs has resulted in support of higher den- sity products, as shown in the L eft versus den- sity logarithmic plot of Figure b.

Section 2. The DRAM memory array and peripheral circuitry suchas decoders, selectors, senseamplifiers, and output drivers are fabricated usingcombinations of n-channel and p-channel MOS transistors. While the density of DRAMs has been approximately quadrupling every three years, neither their access time nor cycle time has im- proved as rapidly.

To increase the DRAM throughput, special techniques such as page mode, static columnmode, or nibble mode have been developed. The faster DRAMs are fabri- cated withspeciallyoptimized processes and in- novative circuit design techniques. In some new DRAMsbeingofferedwith wide on-chip buses, memory locations can be accessed in parallel, e. Trends in standard DRAMdevelop- ment. From [2], with permissionof IEEE. Figure In the last decade of semiconductor mem- ories growth, dynamic randomaccess memories DRAMs have been produced in the largest quantities because of their high density and low cost per bit advantage.

If the power is interrupted, the memory contents are destroyed unless a back-up battery storage systemis main- tained. SRAMoutput widthrangesfrom 1to 32 b wide. Power supply range includes standard 5 V and new 3. The semiconductor memory cells use active element feedback in the form of cross-coupled inverters to store a bit of informa- tion as a logic "one" or a "zero" state.

The active elements in a memorycell needa constant source of de or static power to remain latched in the desired state. The memory cells are arranged in parallel so that all the data can be or. An address multiplexing schemeis used to reducethe numberof input and output pins. As SRAMs have evolved, they have undergone a dramatic increase in their density. Most of this has been due to the scalingdown to smaller geometries. Also, scaling of the feature size reduces the chip area, allowinghigher densitySRAMs to be made more cost effectively.

A significant improvement in cost and power dissipation was achieved by substituting ion- implanted polysilicon load resistors for the two pull-up transistors. At the same time, the concept of power-downmode controlled by the chip enable pin eE also appeared. In this low-voltage standby mode, the standby current for the mixed-MOS parts is typically in the microamp J.. This low-power dissipa- tion in the standby mode opened the potential for high-density battery back-up applications.

However, the mixed-MOS technique provides better scaling advantages and relatively lower power dissipation. The early CMOS RAMs with metal gate technology were mostly used in the aerospace and other high-reliability applications for their wider noise margins, wider supply voltage tolerance, higher operating temperature range, and lower power consumption.

The access and storage transistors are Sec. Ageneral schematic of a SRAM mem- ory cell. The purpose of load devices L is to offset the charge leakage at the drains of the storage and select transistors. When the load transistor is PMOS, the resulting CMOS cell has essentially no current flow a through the cell, except during switching, The depletion load and resistive load have a low level of current flowing through them, and hence the standby power dissipation is always higher than that of the CMOS cell.

Figure a shows the basic CMOS SRAMcell consistingof two transistors and two load elements in a cross-coupled inverterconfig- uration, withtwo select transistors addedto make up a six-transistor cell. There can be several application-specific variations in the basic SRAM cell.

Figure c shows an eight-transistor, double-ended, dual-port static cell. This is useful in cache ar- chitectures, particularly as an embedded mem- ory in a microprocessor chip. Figure d shows a nine-transistor content-addressable memory CAM cell. This is used in applications where knowledge of the contents of the cell, as well as location of the cell, are required. Each memory cell shares electrical connections with all the other cells in its row and column.

The horizontal lines connected to all the cells in a row are called the "word lines," and the vertical lines along which the data flow in and out of the cells are called the "bit lines. Some memories are designed so that a group of four or eight cells can be addressed; the data bus for such memories is called nibble or one byte wide, respectively.

In a RAM, the matrix of parallel memory cells is encircled by the address decoding logic Chap. The memory array nominally uses a square or a rec- tangular organization to minimize the overall chip area and for ease in implementation. The rationale for the square design can be seen by considering a memory device that contains 16K I-bit storage cells. If the array were organized as a single row of 16 Kb, a toK line decoder would be required to allow individ- ual selection of the bits.

However, if the mem- ory is organized as a row X column square, one 7-to line decoder to select a row and another 7-to line decoder to select a column are required.

Each of these decoders can be placed on the sides of the square array. This row X column matrix contains 16, cross-points which allow access to all individual memory bits. Thus, the square memory array or- ganization results in significantly less area for the entire chip. However, the 16K memory may also be organized as a row X column or X 64 array. Most RAMs operate such that the row ad- dress enables all cells along the selected row.

The contents of these cells become available along the column lines. The column address is used to select the particular column containing the desired data bit which is read by the sense amplifier and routed to the data-output pin of the memory chip.

When a RAM is organized to access n bits simultaneously, the data from n columns are selected and gated to n data-output pins simultaneously. The two important time-dependent perfor- mance parameters of a memory are the "read- access time" and the "cycle time. The cycle time is the minimum time that must be al- lowed after the initiation of the read operation or a write operation in a RAM before another read operation can be initiated.

The bit information is stored in the form of voltage lev- els in the cross-coupled inverters. This circuit has two stable states, designated as "1" and "0. The logic HO" state would be the opposite, with point C s low and '6 high. This makes transistors T s and T 6 in all cells of the row switch Han.

A READ operation is performed by start- ing with both the bit and bit lines high and se- lecting the desired word line. At this time, data in the cell will pull one of the bit lines low. The differential signal is detected on the bit and bit lines, amplified, and read out through the output buffer. In reference to Figure , reading from the cell would occur if Band B of the appropri- ate bit lines are high.

If the cell is in state HI," then T is off and T 2 is on. When the word line of the addressed column becomes high, a CUf- rent starts to flow from B through T 6 and T 2 to ground. As a result, the level of 1J becomes lower than B. This differential signal is detected by a differential amplifier connected to the bit and bit lines, amplified, and fed to the output buffer.

The READ opera- tion is nondestructive, and after reading, the logic state of the cell remains unchanged. For a WRITE operation into the cell, data are placed on the bit line and data are placed on the bit line.

Then the word line is activated. This forces the cell into the state represented by the bit lines, so that the new data are stored in the cross-coupled inverters.

In Figure , if the in- formation is to be written into a cell, then B be- comes high and B becomes low for the logic state" I. The word line is then raised, causing the cell to flip into the configuration of the de- sired state. Typical write Sec. Read cir- cuitry generally involves the use of single- ended differential sense amplifiers to read the low-level signals fromthe cells.

The data path is an important consideration with the SRAMs, since the power delay product is largely deter- mined by the load impedance along the data path. The readdata pathcircuitry can be static or dynamic. SRAMs have been designed which turn on or turn off the various sections of data path as needed to reduce the operating power of the device. The internal signals in an outwardly "static" RAM are often generated by a tech- nique called "Address Transition Detection" ATD in which the transition of an address line is detected to generate the various clock signals.

The input circuitry for SRAMs consists of the address decoders, word line drivers, and de- coder controls. Figure shows the various SRAMcircuit elements. RAMs are considered clocked or not clocked, based on the external circuitry. Asyn- chronous nonclocked SRAMs do not require external clocks, and therefore have a very sim- pIe system interface, although they have some internal timing delays. Synchronous clocked SRAMs do require system clocks, but they are faster since all the inputs are clocked into the memory on the edge of the systemclock.

Nowadays, bipolar memories arc primarily used in high- speed applications. Bipolar RAMs are often "word-oriented" and require two-step decoding. For example, in a I-kb X I-b memory orga- nized as a row X colull1n array, the row decoder selects one of the 32 rows, and all of the 32 b the "word" are read out and placed in a register. VariousSRAM circuit elements. Similarly, the data are stored by writing an entire word simultaneously.

Historically, transistor-transistor logic TTL has been the most commonly used bipolar technology. In this configuration, one of the transistors is always conducting, holding the other transistor OFF. When an external voltage forces the OFF tran- sistor intoconduction, the initiallyON transistor turns off and remains in this condition until an- other external voltage resets it. Since only one of the cross-coupled transistors conducts at any given time, the circuit has only two stable states which can be latched to store information in the form of logic 1s and Os.

The cell state is stable until forced to change by an applied voltage. In this figure, the data lines are connected to Q 1 3. From D. Hodges and H. Jackson [37], with permission of McGraw-Hill Inc. Toexplainthe operationof this cell, assumethat a stored 1 corresponds to the state with Q 2 on.

The row selectionrequires that the row voltage shouldbe pulledlow. To write a "1," the voltage on line C is raised, forward-biasing diode Dr: This forces sufficientcurrent throughR1 so that the voltage at node 1 increases to tum on Q2' The current gain of Q1 is sufficiently high, and it remains in saturationso that most of the volt- age drop appears across R 3. When Q 2 turns on, its collector voltage drops rapidly, turning off QI' The currents in RI and R 2 are always much smaller than the current used for writing, so that the voltage drops across R 3 and R 4 are much smaller than Vbe on ' In the standby condition, D 1 and D 2 are reverse-biased.

To read a stored "1," the row is pulled low, and current flows through C through D 2 , R 4 , and Q 2 to R. The re- sulting drop in voltage on C indicates the pres- ence of a stored"1. Another popular bipolar technol- ogy is the emitter-coupled logic EeL. The EeL memories provide very small access times with typical propagation delays of less than 1 ns and clock rates approaching 1 GHz.

This high performance is achieved by preventing the cross-coupled transistors from entering into the saturation region.

Figure shows an EeL memorycell [37]. In this configuration, the data lines are connected to the emitters of the two transistors.

Although both transistors have two.. Emitter-coupledlogic EeL memory cell. Jackson [37], with permis- sion of McGraw-Hili Inc. The operation of the cell is based on using the multiple-emitter transistors as the current switches.

The voltage levels are selected such that these transistors never conduct simultaneously. The read and write operation is controlled by switching the current in the conducting transistor from the row line to the appropriate data line. The basic operation of an ECL cell is ex- plained with Figure To write a "I," the column line C must be held low, which forward-biases the emitter of Ql' regardless of the previous state of the cell.

As a result, the collector-emitter voltage of QI drops quickly, removing the base drive from Q2' When the row voltage returns to the standby levels, QI remains "on," with its base current coming from R 2.

Cell current flows through Q and returns to ground through the line R. The emitters connected to C and Care reverse- biased in the standby condition. To read a stored "1," the cell is selected in the same way as for writing. The emitters connected to R become reverse-biased, and the current flowing in Q1 transfers to the emitter connected to C.

The resulting rise in voltage on C indicates the pres- ence of a stored "I. Weight Levels. Running Levels. Sharma Semiconductor Memories: Technology, Testing, And Reliability in pdf arriving, in that mechanism you forthcoming onto the equitable site. Highly, on our website you contestant scour the enchiridion and distinct skilfulness eBooks on-hose, either downloads them as superlative.

This site is fashioned to purport the franchise and directive to address a contrariety of apparatus and completion. In this paper we will present a review on the development of semiconductor Memories through the most recent decade. Starting demands of low power devices is extending therefore; this is the reason … Expand.

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